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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2002 (all rights reserved) cirrus logic, inc. p.o. box 17847, austin, texas 78760 http://www.cirrus.com cs4341a 24-bit, 192 khz stereo dac with volume control features 101 db dynamic range -91 db thd+n +3.3 v or +5 v power supply 50 mw with 3. 3v supply low clock jitter sensitivity filtered line level outputs on-chip digital de-emphasis for 32, 44.1, and 48 khz atapi mixing digital volume control with soft ramp ? 94 db attenuation ? 1 db step size ? zero crossing click-free transitions up to 200 khz sample rates automatic mode detection for sample rates between 4 and 2 0 0khz pin compatible with the cs4341 description the cs4341a is a complete stereo digital-to-analog sys- tem including digital interpolation, fourth-order delta- sigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing and analog filtering. the advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and tempera- ture and a high tolerance to clock jitter. the cs4341a accepts data at all standard audio sample rates up to 192 khz, consumes very little power, oper- ates over a wide power supply range and is pin compatible with the cs4341, as described in section 3.1. these features are ideal for dvd audio p layers. ordering information CS4341A-KS 16-pin soic, -10 to 70 c cdb4341a evaluation board volume control interpolation filter ? dac analog filter control port interface volume control interpolation filter analog filter serial audio interface scl/cclk mutec ad0/cs aouta aoutb rst lrck sdin mclk sda/cdin ? dac external mute control sclk mixer 2 aug ?02 ds582pp1
cs4341a 2 ds582pp1 table of contents 1. pin description ........................................................................................................... ........ 5 2. typical connection diagram ...................................................................................... 6 3. applications .............................................................................................................. .......... 7 3.1 upgrading from the cs4341 to the cs4341a .................................................................... 7 3.2 sample rate range/operational mode detect .................................................................. 7 3.2.1 auto-detect enabled ............................................................................................. 7 3.2.2 auto-detect disabled ............................................................................................ 7 3.3 system clocking ........................................................................................................... ..... 8 3.4 digital interface format .................................................................................................. .... 8 3.5 de-emphasis control ....................................................................................................... .. 9 3.6 recommended power-up sequence ................................................................................. 9 3.7 popguard ? transient control ........................................................................................... 10 3.7.1 power-up ............................................................................................................. 10 3.7.2 power-down ........................................................................................................ 10 3.7.3 discharge time ................................................................................................... 10 3.8 grounding and power supply arrangements .................................................................. 10 3.9 control port interface .................................................................................................... ... 11 3.9.1 map auto increment ........................................................................................... 11 3.9.2 i2c mode ............................................................................................................. 11 3.9.2a i2c write .............................................................................................. 11 3.9.2b i2c read .............................................................................................. 12 3.9.3 spi mode ............................................................................................................ 13 3.9.3a spi write .............................................................................................. 13 3.10 memory a ddress pointer (map) .............................................................................. 14 3.10.1 incr (auto map increment enable) ............................................................................ 14 3.10.2 map (memory address pointer) .................................................................................. 14 4. register quick reference .......................................................................................... 14 contacting cirrus logic support for a com plete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm important notice "preliminary" product information describes pr oducts that are in pr oduction, but for which full characterizat ion data is not yet available. "advance" pr oduct infor- mation describes pr oducts that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries ("cirrus") believe that the infor- mation contained in this document is accurate and reliable. however, the information is subject to change without notice and i s provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that informat ion being relied on is current and complete. all products are sold subject to the terms and c onditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. no responsi bility is as sumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work righ ts, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights of the information contained herein and gives c onsent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other parts of cirrus. this consent does not ex t end to other copying such as copying for general distribution, advertising or promoti onal purposes, or for creating any work for resale. an export permit needs to be obtai ned from the com petent authorit ies of the japanese government if any of the products or t echnologies described in this ma- terial and controlled under the "foreign excha nge and foreign tr ade law" is to be exported or taken out of japan. an exp ort license and/or quota needs to be obtained from the competent authorities of the chinese government if any of the products or technologies described in this mate rial is subject to the prc foreign trade law and is to be exported or taken out of the prc. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("critical applications"). cirrus products are not designed, authorized, or warrant- ed to be suitable for use in life-support devices or systems or other critical applications. inclusion of cirrus pro ducts in such applications is understood to be fully at the customer's risk. purchase of i 2 c components of cirrus logic, inc., or one of its subli censed a ssoc iated companies conveys a license under the p hillips i 2 c patent rights to use those components in a standard i 2 c system. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trade- marks or service marks of their respective owners.
cs4341a ds582pp1 3 5. register description .................................................................................................... 15 5.1 mode control 1 (address 00h).......................................................................................... 15 5.2 mode control 2 (address 01h).......................................................................................... 15 5.3 transition and mixing control (address 02h).................................................................... 17 5.4 channel a volume control (address 03h) ........................................................................ 20 5.5 channel b volume control (address 04h) ........................................................................ 20 6. characteristics and specifications ...................................................................... 21 analog characteristics (CS4341A-KS) ..................................................................... 21 combined interpolation & on-chip analog filter response ........................ 23 switching specifications - serial audio interface .......................................... 26 switching specifications - control port interface ....................................... 27 switching specifications - control port interface ....................................... 28 dc electrical characteristics ................................................................................ 29 digital input characteristics ................................................................................... 29 digital interface specifications ............................................................................. 29 thermal characteristics and specifications .................................................... 29 recommended operating specification .............................................................. 30 absolute maximum ratings ......................................................................................... 30 7. parameter definitions .................................................................................................. 31 total harmonic distortion + noise (thd+n) .......................................................................... 31 dynamic range .................................................................................................................. .... 31 interchannel isolation ......................................................................................................... .... 31 interchannel gain mismatch ................................................................................................... 31 gain error ..................................................................................................................... .......... 31 gain drift ..................................................................................................................... ........... 31 8. references ................................................................................................................ ........ 31 9. package dimensions ...................................................................................................... 32 list of figures figure 1. typical connection diagram .......................................................................................... 6 figure 2. i 2 s data ........................................................................................................................ .8 figure 3. left justified up to 24-bit data ..................................................................................... .. 9 figure 4. right justified data ................................................................................................. ....... 9 figure 5. de-emphasis curve .................................................................................................... ... 9 figure 6. control port timing, i2c mode .................................................................................... 12 figure 7. control port timing, spi mode .................................................................................... 13 figure 8. atapi block diagram .................................................................................................. 19 figure 9. output test load ..................................................................................................... .... 22 figure 10. maximum loading ..................................................................................................... ... 22 figure 11. single-speed stopband rejection ............................................................................... 24 figure 12. single-speed transition band ..................................................................................... 24 figure 13. single-speed transition band (detail) ......................................................................... 24 figure 14. single-speed passband ripple ................................................................................... 24 figure 15. double-speed stopband rejection .............................................................................. 24 figure 16. double-speed transition band .................................................................................... 24 figure 17. double-speed transition band (detail) ....................................................................... 25 figure 18. double-speed passband ripple .................................................................................. 25 figure 19. serial input timing ................................................................................................. ...... 26 figure 20. control port timing - i2c mode ................................................................................... 27 figure 21. control port timing - spi mode ................................................................................... 28
cs4341a 4 ds582pp1 list of tables table 1. cs4341a auto-detect ................................................................................................... ....... 7 table 2. cs4341a mode select ................................................................................................... ...... 7 table 3. single-speed m ode st andard fr equencies.......................................................................... 8 table 4. double-s peed m ode s tandard frequencies........................................................................ 8 table 5. quad-speed m ode s tandard frequencies........................................................................... 8 table 7. atapi decode.......................................................................................................... .......... 18 table 8. example digital volume settings ....................................................................................... 20
cs4341a ds582pp1 5 1. pin description 15 2 14 3 13 4 16 1 11 6 10 7 9 8 12 5 rst mutec sdin aouta sclk va lrck agnd mclk aoutb scl/cclk ref_gnd sda/cdin vq ad0/cs filt+ pin name # pin description rst 1 reset ( input ) - powers down device when enabled. sdin 2 serial audio data ( input ) - input for two?s complement serial audio data. sclk 3 serial clock ( input ) -serial clock for the serial audio interface. lrck 4 left right clock ( input ) - determines which channel, left or right, is currently active on the serial audio data line. mclk 5 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. scl/cclk 6 serial control port clock ( input ) - serial clock for the control port interface. sda/cdin 7 serial control data i/o ( input / output ) - input/output for i 2 c data. input for spi data. ad0/cs 8 address bit / chip select ( input ) - chip address bit in i 2 c mode. control signal used to select the chip in spi mode. filt+ 9 positive voltage reference ( output ) - positive voltage reference for the internal sampling cir- cuits. vq 10 quiescent voltage ( output ) - filter connection for internal quiescent reference voltage. ref_gnd 11 reference ground ( input ) - ground reference for the internal sampling circuits. aoutr aoutl 12 15 analog outputs ( output ) - the full scale analog output level is specified in the analog charac- teristics table. agnd 13 analog ground ( input ) - ground reference. va 14 power ( input ) - positive power for the analog, d igital, control port interface, and serial audio interface sections. mutec 16 mute control ( output ) - control signal for optional mute circuit.
cs4341a 6 ds582pp1 2. typical connection diagram 13 serial audio data processor external clock mclk agnd ao utb cs4341a sdin lrck va ao uta 3 4 5 14 0.1 f + 1f 12 +3.3v or +5.0v 3.3 f 3.3 f 10 k ? c c 560 ? 560 ? + + micro- controlled configuration 8 6 7 sclk 1 2 scl/cclk sda/cdin ad0/cs rst mutec 16 optional mute circuit 15 1f 0.1 f audio output a audio output b r l r l + + 10 k ? .1 f 1f 9 10 11 ref_gnd filt+ vq c= 4 fs(r 560) l r 560 l + figure 1. typical connection diagram
cs4341a ds582pp1 7 3. applications 3.1 upgrading from the cs4341 to the cs4 341a the cs4341a is pin and functionally compatible with all cs4341 designs, operating at the standard audio sample rates, that use pin 3 as a serial clock input. in addition to the features of the cs4341, the cs4341a supports standard sample rates up to 192 khz, as well as automatic mode detection for sample rates be- tween 4 and 200 khz. the automatic speed mode detection feature allows sample rate changes between single, double and quad-speed modes without external intervention. the cs4341a does not support an internal serial clock mode or sample rates between 50 khz and 84 khz (unless otherwise stated), as does the cs4341. 3.2 sample rate range/operational mode detect the device operates in one of three operational modes. the allowed sample rate range in each mode will depend on whether the auto-detect defeat bit is enabled/disabled. 3.2.1 auto-detect enabled the auto-detect feature is enabled by default in the control port register 5.1. in this state, the cs4341a will auto-detect the correct mode when the input sample rate (f s ), defined by the lrck frequency, falls within one of the ranges illustrated in table 1. sample rates outside the specified range for each mode are not supported. 3.2.2 auto-detect disabled the auto-detect feature can be defeated via the control port register 5.1. in this state, the cs4341a will not auto-detect the correct mode based on the input sample rate (f s ). the operational mode must be set appropriately if f s falls within one of the ranges illustrated in table 2. please refer to section 5.1.1 for implementation details. sample rates outside the specified range for each mode are not supported. input sample rate (f s )mode 4khz - 50khz single speed mode 84khz - 100khz double speed mode 170khz - 200khz quad speed mode table 1. cs4341a auto-detect mc1 mc0 input sample rate (f s )mode 0 0 4khz - 50khz single speed mode 0 1 50khz - 100khz double speed mode 1 0 100khz - 200khz quad speed mode table 2. cs4341a mode select
cs4341a 8 ds582pp1 3.3 system clocking the device requires external generation of the master (mclk), left/right (lrck) and serial (sclk) clocks. the lrck, defined also as the input sample rate (f s ), must be synchronously derived from the mclk according to specified ratios. the specified ratios of mclk to lrck for each speed mode, along with several standard audio sample rates and the required mclk frequency, are illustrated in tables 3-5. * requires mclkdiv bit = 1 in the mode control 1 register (address 00h). 3.4 digital interface format the device will accept audio samples in several digital interface formats. the desired format is selected via the dif0, dif1 and dif2 bits in the mode control 2 register (see section 5.2.2) . for an illustration of the required relationship between lrck, sclk and sdin, see figures 2-4. sample rate (khz) mclk (mhz) 256x 384x 512x 768x 1024x* 32 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 table 3. single-speed mode standard frequencies sample rate (khz) mclk (mhz) 128x 192x 256x 384x 512x* 64 8.1920 12.2880 16.3840 24.5760 32.7680 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 table 4. double-speed mode standard frequencies sample rate (khz) mclk (mhz) 128x 192x 256x* 176.4 22.5792 33.8688 45.1584 192 24.5760 36.8640 49.1520 table 5. quad-speed mode standard frequencies lrck sclk left channel right channel sdin +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb lsb figure 2. i 2 s data
cs4341a ds582pp1 9 3.5 de-emphasis control the device includes on-chip digital de-emphasis. the mode control 2 bits select either the 32, 44.1, or 48 khz de-emphasis filter. figure 5 shows the de-emphasis curve for f s equal to 44.1 khz. the frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, fs. please see section 5.2.3 for the desired de-emphasis control. note: de-emphasis is only available in single-speed mode. 3.6 recommended power-up sequence 1. hold rst low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequences, as discussed in section 3.2. in this state, the control port is reset to its default settings and vq will remain low. 2. bring rst high. the device will remain in a low power s tate with vq low. 3. load the desired register settings while keeping the pdn bit set to 1. 4. set the pdn bit to 0. this will initiate the power-up sequence, which lasts approximatel y 50s when the por bit is set to 0. if the por bit is set to 1, see section 3.7 for a complete description of power-up timing. lrck sclk left channel right channel sdin +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 lsb msb lsb figure 3. left justified up to 24-bit data lrck sclk left channel sdin -6 -5 -4 -3 -2 -1 -7 +1 +2 +3 +4 +5 32 clocks msb right channel lsb msb +1 +2 +3 +4 +5 lsb -6 -5 -4 -3 -2 -1 -7 msb figure 4. right justified data gain db -1 0db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 kh z 10.61 khz figure 5. de-emphasis curve
cs4341a 10 ds582pp1 3.7 popguard ? transient control the cs4341a uses popguard ? technology to minimize the effects of output transients during power-up and power-down. this technol ogy, when used with external dc-blocking capacitors in series with the au- dio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. it is activated inside the dac when the pdn bit or the rst pin is enabled/disabled and requires no other external control, aside from choosing the appropriate dc-blocking capacitors. 3.7.1 power-up when the device is initially powered-up, the audio outputs, aoutl and aoutr, are clamped to agnd. following a delay of approximately 1000 s ample periods, each output begins to ramp to- ward the quiescent voltage. approximately 10,000 lrck cycles later, the outputs reach v q and audio output begins. this gradual voltage ramping allows time for the external dc-blocking capac- itors to charge to the quiescent voltage, minimizing the power-up transient. 3.7.2 power-down to prevent transients at power-down, the device must first enter its power-down state by enabling rst or pdn. when this occurs, audio output ceases and the internal output buffers are disconnect- ed from aoutl and aoutr. in their place, a soft-start current sink is substituted which allows the dc-blocking capacitors to slowly discharge. once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on. 3.7.3 discharge time to prevent an audio transient at the next power-on, it is necessary to ensure that the dc-blocking capacitors have fully discharged before turning on the power or exiting the power-down state. if not, a transient will occur when the audio outputs are initially clamped to agnd. the time that the device must remain in the power-down state is related to the value of the dc-blocking capacitance. for example, with a 3.3 f capacitor, the minimum power-down time will be approximately 0.4 seconds. 3.8 grounding and power supply arrangements as with any high resolution converter, the cs4341a requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. figure 1 shows the recommended power arrangements, with va connected to a clean supply. if the ground planes are split between digital ground and analog ground, ref_gnd & agnd should be connected to the analog ground plane. decoupling capacitors should be as close to the dac as possible, with the low value ceramic capacitor being the closest. to further minimze impedance, these capacitors should be located on the same layer as the dac. all signals, especially clocks, should be kept away from the filt+ and vq pins in order to avoid unwant- ed coupling into the modulators. the filt+ and vq decoupling capacitors, particularly the 0. 1f, must be positioned to minimize the electrical path from filt+ to ref_gnd (and vq to ref_gnd), and should also be located on the same layer as the dac. the cdb4341a evaluation board demonstrates the optimum layout and power supply arrangements.
cs4341a ds582pp1 11 3.9 control port interface the control port is used to load all the internal register settings (see section 5). the operation of the control port may be completely asynchronous with the audio sample rate. however, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port operates in one of two modes: i 2 c or spi. notes: mclk must be applied during all i 2 c communication. 3.9.1 map auto increment the device has map (memory address pointer) auto increment capability enabled by the incr bit (also the msb) of the map. if incr is set to 0, map will stay constant for successive i 2 c writes or reads, and spi writes. if incr is set to 1, map will auto increment after each byte is written, allowing block reads or writes of successive registers. 3.9.2 i 2 c mode in the i 2 c mode, data is clocked into and out of the bi-directional serial control data line, sda, by the serial control port clock, scl (see figure 6 for the clock to data relationship). there is no cs pin. pin ad0 enables the user to alter the chip address (001000[ad0][r/w ]) and should be tied to va or gnd as required, before powering up the device. if the device ever detects a high to low transition on the ad0/cs pin after power-up, spi mode will be selected. 3.9.2a i 2 c write to write to the device, follow the procedure below while adhering to the control port switching specifications in section 7. 1) initiate a start condition to the i 2 c bus followed by the address byte. the upper 6 bits must be 001000. the seventh bit must match the setting of the ad0 pin, and the eighth must be 0. the eighth bit of the address byte is the r/w bit. 2) wait for an acknowledge (ack) from the part, then write to the memory address pointer, map. this byte points to the register to be written. 3) wait for an acknowledge (ack) from the part, then write the desired data to the register pointed to by the map. 4) if the incr bit (see section 3.9.1) is set to 1, repeat the previous step until all the desired registers are written, then initiate a stop condition to the bus. 5) if the incr bit is set to 0 and further i 2 c writes to other registers are desired, it is nec- essary to initiate a repeated start condition and follow the procedure detailed from step 1. if no further writes to other registers are desired, initiate a stop condition to the bus.
cs4341a 12 ds582pp1 3.9.2b i 2 c read to read from the device, follow the procedure below while adhering to the control port switching specifications . 1) initiate a start condition to the i 2 c bus followed by the address byte. the upper 6 bits must be 001000. the seventh bit must match the setting of the ad0 pin, and the eighth must be 1. the eighth bit of the address byte is the r/w bit. 2) after transmitting an acknowledge (ack), the device will then transmit the contents of the register pointed to by the map. the map register will contain the address of the last register written to the map, or the default address (see section 8.3) if an i 2 c read is the first operation performed on the device. 3) once the device has transmitted the contents of the register pointed to by the map, issue an ack. 4) if the incr bit is set to 1, the device w ill continue to transmit the contents of successive registers. continue providing a clock and issue an ack after each byte until all the desired registers are read, then initiate a stop condition to the bus. 5) if the incr bit is set to 0 and further i 2 c reads from other registers are desired, it is nec- essary to initiate a repeated start condition and follow the procedure detailed from step 1. if no further reads from other registers are desired, initiate a stop condition to the bus. sda scl 001000 ad0 r/w start ack data 1-8 ack data 1-8 ack stop note note: if operation is a write, this byte contains the memory address po inter, map. if operation is a read, this byte contains the data of the register pointed to by the map. figure 6. control port timing, i 2 c mode
cs4341a ds582pp1 13 3.9.3 spi mode in spi mode, data is clocked into the serial control data line, cdin, by the serial control port clock, cclk (see figure 7 for the clock to data relationship). there is no ad0 pin. pin cs is the chip select signal and is used to control spi writes to the control port. when the device detects a high to low transition on the ad0/cs pin after power-up, spi mode will be selected. all signals are inputs and data is c locked in on the rising edge of cclk. 3.9.3a spi write to write to the device, follow the procedure below while adhering to the control port switching specifications in section 6. 1) bring cs low. 2) the address byte on the cdin pin must then be 00100000. 3) write to the memory address pointer, map. this byte points to the register to be written. 4) write the desired data to the register pointed to by the map. 5) if the incr bit (see section 3.9.1) is set to 1, repeat the previous step until all the desired registers are written, then bring cs high. 6) if the incr bit is set to 0 and further spi writes to other registers are desired, it is nec- essary to bring cs high, and follow the procedure detailed from step 1. if no further writes to other registers are desired, bring cs high. map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 0010000 figure 7. control port timing, spi mode
cs4341a 14 ds582pp1 3.10 memory address pointer (map) 4. register quick reference addr function 7 6 5 4 3 2 1 0 0h mode control 1 reserved mc1 mc0 reserved reserved autod mclkdiv reserved default 00000000 1h mode control 2 amute dif2 dif1 dif0 dem1 dem1 por pdn default 10000011 2h transition and mixing control a = b soft zero cross atapi4 atapi3 atapi2 atapi1 atapi0 default 00000000 3h channel a volume control mutea vola6 vola5 vola4 vola3 vola2 vola1 vola0 default 00000000 4h channel b volume control muteb volb6 volb5 volb4 volb3 volb2 volb1 volb0 default 00000000 3.10.1 incr (auto map increment enable) default = ?0? 0 - disabled 1 - enabled 3.10.2 map (memory address pointer) default = ?000? 76543210 incr reserved reserved reserved reserved map2 map1 map0 00000000
cs4341a ds582pp1 15 5. register description note: all registers are read/write in i 2 c mode and write only in spi mode, unless otherwise stated. 5.1 mode control 1 (address 00h) 5.1.1 speed mode control (mc) bit 5-6 default = 00 00 - single-speed mode 01 - double-speed mode 10 - quad-speed mode the operational speed mode must be set if the auto-detect defeat bit is enabled (autod = 1). these bits are ignored if the auto-detect defeat is disabled (autod = 0). 5.1.2 auto-detect defeat (autod) bit 2 default = 0 0 - disabled 1 - enabled the auto-detect function can be defeated to allow sample rate changes from 50 to 84 khz, and from 100 to 170 khz. the operational speed mode must be set via the speed mode control bits (see section 5.1.1) if the auto-detect feature is defeated. 5.1.3 mclk divide-by-2 (mclkdiv) bit 1 default = 0 0 - disabled 1 - enabled function: the mclkdiv bit enables a circuit which divides the externally applied mclk signal by 2. 5.2 mode control 2 (address 01h) 76543210 reserved mc1 mc0 reserved reserved autod mclkdiv reserved 00000000 76543210 amute dif2 dif1 dif0 dem1 dem0 por pdn 10000011
cs4341a 16 ds582pp1 5.2.1 auto-mute (amute) bit 7 default = 1 0 - disabled 1 - enabled function: the digital-to-analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. a single sample of non-zero data will release the mu te. detection and mut- ing is done independently for each channel. the quiescent voltage on the output will be retained and the mute control pin will go active during the mute period. the muting function is affected, similiar to volume control changes, by the soft and zero cross bits in the transition and mixing control (address 02h) register. 5.2.2 digital interface format (dif) bit 4-6 default = 000 - format 0 (i 2 s, up to 24-bit data) function: the required relationship between the left/right clock, se rial clock and ser ial data is defined by the digital interface format and the options are detailed in figures 2-4. 5.2.3 de-emphasis control (dem) bit 2-3 default = 00 00 - disabled 01 - 44.1 khz 10 - 48 khz 11 - 32 khz function: implementation of the standard 15 s/50 s digital de-emphasis filter response, figure 5, requires re- configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 khz sample rates. note: de-emphasis is only available in single-speed mode. dif2 dif1 dif0 description format figure 000i 2 s, up to 24-bit data 1 2 0 0 1 identical to format 1 1 2 0 1 0 left justified, up to 24-bit data, 2 3 0 1 1 right justified, 24-bit data 3 4 1 0 0 right justified, 20-bit data 4 4 1 0 1 right justified, 16-bit data 5 4 1 1 0 right justified, 18-bit data 6 4 1 1 1 identical to format 1 1 2 table 6. digital interface format
cs4341a ds582pp1 17 5.2.4 popguard ? transient control (por) bit 1 default = 1 0 - disabled 1 - enabled function: the popguard ? transient control allows the quiescent voltage to slowly ramp to and from 0 volts to the quiescent voltage during power-on or power-down. please refer to section 3.7 for implementation details. 5.2.5 power down (pdn) bit 0 default = 1 0 - disabled 1 - enabled function: the device will enter a low-power state when this function is enabled. the power-down bit defaults to ?enabled? on power-up and must be disabled before normal operation can occur. the contents of the control registers are retained in this mode. 5.3 transition and mixing control (address 02h) 5.3.1 channel a volume = channel b volume (a = b) bit 7 default = 0 0 - disabled 1 - enabled fucntion: the aouta and aoutb volume levels are independently controlled by the a and the b channel vol- ume control bytes when this function is disabled. the volume on both aouta and aoutb are de- termined by the a channel volume control byte and the b channel byte is ignored when this function is enabled. 76543210 a = b szc1 szc0 atapi4 atapi3 atapi2 atapi1 atapi0 01001001
cs4341a 18 ds582pp1 5.3.2 soft ramp and zero cross control (szc) bit 5-6 default = 10 00 - immediate changes 01 - changes on zero crossings 10 - soft ramped changes 11 - soft ramped changes on zero crossings fucntion: immediate changes when immediate changes is selected all level changes w ill take effect immediately in one step. changes on zero crossings changes on zero crossings dictates that signal level changes, either by attenuation changes or mut- ing, will occur on a signal zero crossing to minimize audible artifacts. the requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independent- tly monitored and implemented for each channel. soft ramped changes soft ramped changes allows level changes, both muting and attenuation, to be implemented by in- crementally ramping, in 1/8 db steps, from the current level to the new level at a rate of 1db per 8 left/right clock periods. soft ramped changes on zero crossings soft ramped changes on zero crossings dictates that signal level changes, either by att enuation changes or muting, will occur in 1/8 db steps implemented on a signal zero crossing. the 1/8 db level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not enc ounter a zero cr ossing. the zero cross function is indepently monitored and implemented for each channel. 5.3.3 atapi channel mixing and muting (atapi) bit 0-4 default = 01001 - aouta = left channel, aoutb = right channel (stereo) fucntion: the cs4341a implements the channel mixing functions of the atapi cd-rom specification. refer to table 7 and figure 8 for additional information. atapi4 atapi3 atapi2 atapi1 atapi0 aouta aoutb 00000 mute mute 00001 mute br 00010 mute bl 00011 mute b[(l+r)/2] 00100 ar mute 00101 ar br 00110 ar bl 00111 ar b[(l+r)/2] 01000 al mute 01001 al br table 7. atapi decode
cs4341a ds582pp1 19 01010 al bl 01011 al b[(l+r)/2] 01100 a[(l+r)/2] mute 01101 a[(l+r)/2] br 01110 a[(l+r)/2] bl 0 1 1 1 1 a[(l+r)/2] b[(l+r)/2] 10000 mute mute 10001 mute br 10010 mute bl 1 0 0 1 1 mute [(al+br)/2] 10100 ar mute 10101 ar br 10110 ar bl 1 0 1 1 1 ar [(bl+ar)/2] 11000 al mute 11001 al br 11010 al bl 1 1 0 1 1 al [(al+br)/2] 1 1 1 0 0 [(al+br)/2] mute 1 1 1 0 1 [(al+br)/2] br 1 1 1 1 0 [(bl+ar)/2] bl 1 1 1 1 1 [(al+br)/2] [(al+br)/2] atapi4 atapi3 atapi2 atapi1 atapi0 aouta aoutb table 7. atapi decode (continued) ? a channel volume control aouta aoutb left channel audio data right channel audio data b channel volume control mute mute figure 8. atapi block diagram
cs4341a 20 ds582pp1 5.4 channel a volume control (address 03h) 5.5 channel b volume control (address 04h) 5.5.1 mute (mute) bit 7 default = 0 0 - disabled 1 - enabled fucntion: the digital-to-analog converter output will mute when enabled. the quiescent voltage on the output will be retained. the muting function is affected, similiar to attenuation changes, by the soft and zero cross bits in the transition and mixing control (address 02h) register. the mutec will go active dur- ing the mute period if the mute function is enabled for both c hannels. 5.5.2 volume (volx) bit 0-6 default = 0 db (no attenuation) function: the digital volume control allows the user to attenuate the signal in 1 db increments from 0 to -90 db. volume settings are decoded as shown in table 8. the volume changes are implemented as dictated by the soft and zero cross bits in the transition and mixing control (address 02h) register. all volume settings less than - 94 db are equivalent to enabling the mute bit. 76543210 mutex volx6 volx5 volx4 volx3 volx2 volx1 volx0 00000000 binary code decimal value volume setting 0000000 0 0 db 0010100 20 -20 db 0101000 40 -40 db 0111100 60 -60 db 1011010 90 -90 db table 8. example digital volume settings
cs4341a ds582pp1 21 6. characteristics and specifications analog characteristics (CS4341A-KS) (test conditions (unless otherwise specified): input test signal is a 997 hz sine wave at 0 dbfs; measurement bandwidth is 10 hz to 20 khz; test load r l = 10k ? , c l = 10 pf (see figure 9). t ypical performance characteristics are derived from measurements taken at t a = 25 c, va = 5.0v and 3.3v. min/max performance characteristics are guaranteed over the spe cified operating temperature and voltages. ) parameter va = 5.0v va = 3.3v min typ max min typ max unit single-speed mode fs = 48khz dynamic range (note 1) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted 92 95 - - 98 101 92 95 - - - - 88 91 - - 94 97 92 95 - - - - db db db db total harmonic distortion + noise (note 1) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -91 -78 -38 -90 -72 -32 -85 - - - - - - - - - - - -94 -74 -34 -91 -72 -32 -88 - - - - - db db db db db db double-speed mode fs = 96khz dynamic range (note 1) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted 92 95 - - 98 101 92 95 - - - - 88 91 - - 94 97 92 95 - - - - db db db db total harmonic distortion + noise (note 1) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -91 -78 -38 -90 -72 -32 -85 - - - - - - - - - - - -94 -74 -34 -91 -72 -32 -88 - - - - - db db db db db db quad-speed mode fs = 192khz dynamic range (note 1) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted 92 95 - - 98 101 92 95 - - - - 88 91 - - 94 97 92 95 - - - - db db db db total harmonic distortion + noise (note 1) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -91 -78 -38 -90 -72 -32 -85 - - - - - - - - - - - -94 -74 -34 -91 -72 -32 -88 - - - - - db db db db db db
cs4341a 22 ds582pp1 analog characteristics (CS4341A-KS) (continued) notes: 1. one-half lsb of triangular pdf dither is added to data. 2. refer to figure 10. . parameters symbol min typ max units dynamic performance for all modes interchannel isolation (1 khz) - 102 - db dc accuracy interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c analog output characteristics and specifications full scale output voltage 0.6va 0.7va 0.8va vpp output impedance - 100 - ? minimum ac-load resistance (note 2) r l -3-k ? maximum load capacitance (note 2) c l - 100 - pf aoutx agnd 3.3 f v out r l c l + figure 9. output test load 100 50 75 25 2.5 5 10 15 safe operating region capacitive load -- c (pf) l resistive load -- r (k ? ) l 125 3 20 figure 10. maximum loading
cs4341a ds582pp1 23 combined interpolation & on-chip analog filter response (the filter characteristics and the x-axis of the response plots have been normalized to the sample rate (fs) and can be referenced to the desired sample rate by multiplying the given characteristic by fs.) notes: 3. for single-speed mode, the measurement bandwidth is 0.5465 fs to 3 fs. for double-speed mode, the measurement bandwidth is 0.577 fs to 1.4 fs. 4. de-emphasis is only available in single-speed mode. parameter min typ max unit single-speed mode - (4khz to 50khz sample rates) passband to -0.05 db corner to -3 db corner 0 0 - - 0.4535 0.4998 fs fs frequency response 10 hz to 20 khz -0.02 - +0.08 db stopband 0.5465 - - fs stopband attenuation (note 3) 50 - - db group delay - 9/fs - s passband group delay deviation 0 - 20 khz - 0.36/fs - s de-emphasis error (relative to 1 khz) fs = 32 khz (note 4) fs = 44.1 khz fs = 48 khz - - - - - - +0.2/-0.1 +0.05/-0.14 +0/-0.22 db db db double-speed mode - (50khz to 100khz sample rates) passband to -0.1 db corner to -3 db corner 0 0 - - 0.4621 0.4982 fs fs frequency response 10 hz to 20 khz -0.06 - +0.2 db stopband 0.577 - - fs stopband attenuation (note 3) 55 - - db group delay - 4/fs - s passband group delay deviation 0 - 40 khz 0 - 20 khz - - 1.39/fs 0.23/fs - - s s quad-speed mode - (100khz to 200khz sample rates) frequency response 10 hz to 20 khz -1 - 0 db group delay - 3/fs - s
cs4341a 24 ds582pp1 figure 11. single-speed stopband rejection figure 12. single-speed transition band figure 13. single-speed transition band (detail) figure 14. single-speed passband ripple figure 15. double-speed stopband r ejection figure 16. double-speed transition band
cs4341a ds582pp1 25 figure 17. double-speed transition band (detail) figure 18. double-speed passband ripple
cs4341a 26 ds582pp1 switching specifications - serial audio interface parameters symbol min max units mclk frequency 1.024 51.2 mhz mclk duty cycle 45 55 % input sample rate single-speed mode double-speed mode quad-speed mode fs fs fs 4 50 100 50 100 200 khz khz khz lrck duty cycle 40 60 % sclk pulse width low t sclkl 20 - ns sclk pulse width high t sclkh 20 - ns sclk frequency mclkdiv disabled - hz mclkdiv enabled - hz sclk rising to lrck edge delay t slrd 20 - ns sclk rising to lrck edge setup time t slrs 20 - ns sdin valid to sclk rising setup time t sdlrs 20 - ns sclk rising to sdin hold time t sdh 20 - ns sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdin sclk lrck figure 19. serial input timing mclk 2 ----------------- - mclk 4 ----------------- -
cs4341a ds582pp1 27 switching specifications - control port interface (inputs: logic 0 = agnd, logic 1 = va) notes: 5. data must be held for sufficient time to bridge the transition time, t fc , of scl. parameter symbol min max unit i 2 c mode scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 5) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc , t rc -1s fall time scl and sda t fc , t fc - 300 ns setup time for stop condition t susp 4.7 - s t buf t hdst t lo w t hdd t high t sud stop start sda scl t irs rst t hdst t rc t fc t sust t susp start stop repeated t rd t fd t ack figure 20. control port timing - i 2 c mode
cs4341a 28 ds582pp1 switching specifications - control port interface (continued) notes: 6. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 7. data must be held for sufficient time to bridge the transition time of cclk. 8. for f sclk < 1 mhz. parameter symbol min max unit spi mode cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 6) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 7) t dh 15 - ns rise time of cclk and cdin (note 8) t r2 - 100 ns fall time of cclk and cdin (note 8) t f2 - 100 ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 21. control port timing - spi mode
cs4341a ds582pp1 29 dc electrical characteristics (agnd = 0v; all voltages with respect to agnd.) digital input characteristics (agnd = 0v; all voltages with respect to agnd.) digital interface specifications (gnd = 0 v; all voltages with respect to gnd.) thermal characteristics and specifications parameters symbol min typ max units normal operation (note 9) power supply current va = 5.0v va = 3.3v i a - - 18 15 25 20 ma ma power dissipation va = 5.0v va = 3.3v - - 90 50 125 100 mw mw power-down mode (note 10) power supply current va = 5.0v va = 3.3v i a - - 60 35 - - a a power dissipation va = 5.0v va = 3.3v - - 0.3 0.1 - - mw mw all modes of operation power supply rejection ratio (note 11) 1 khz 60 hz psrr - - 60 40 - - db db v q nominal voltage output impedance maximum allowable dc current source/sink - - - 0.5va 250 0.01 - - - v k ? ma filt+ nominal voltage output impedance maximum allowable dc current source/sink - - - va 250 0.01 - - - v k ? ma mutec low-level output voltage - 0 - v mutec high-level output voltage - va - v maximum mutec drive current - 3 - ma parameters symbol min typ max units input leakage current i in --10 a input capacitance - 8 - pf parameters symbol min max units interface voltage supply = 3.3v or 5.0v high-level input voltage v ih 2.0 - v low-level input voltage v il -0.8 v parameters symbol min typ max units package thermal resistance ja - 125 - c/watt ambient operating temperature (power applied) t a -10 - +70 c
cs4341a 30 ds582pp1 recommended operating specification absolute maximum ratings (agnd = 0 v; all voltages with respect to agnd. operation beyond these limits may result in permanent damage to the device. normal operation is not guarant eed at these extremes.) notes: 9. normal operation is defined as rst = hi with a 997 hz, 0dbfs input sampled at the highest f s for each speed mode, and open outputs, unless otherwise spe cified. 10. power down mode is defined as rst = lo with all clocks and data li nes held static. 11. valid with the recommended capacitor values on filt+ and vq as shown in figure 1. increasing the capacitance will also increase the psrr. 12. any pin except supplies. parameters symbol min typ max units dc power supply analog va 2.7 4.5 3.3 5 3.6 5.5 v v parameters symbol min max units dc power supply va -0.3 6.0 v input current (note 12) i in -10ma digital input voltage v ind -0.3 va+0.4 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c
cs4341a ds582pp1 31 7. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10hz to 20khz), including distortion comp onents. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not affect the measurement. this m easurement techni que has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries association of j apan, eiaj cp- 307. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with tem pera ture. units in ppm/c. 8. references 1) cdb4341a evaluation board datasheet 2) ?the i 2 c bus specification: version 2.1? philips semiconductors, january 2000. http://www.semiconductors. phili ps.com
cs4341a 32 ds582pp1 9. package dimensions inches millimeters dim min max min max a 0.053 0.069 1.35 1.75 a1 0.004 0.010 0.10 0.25 b 0.013 0.020 0.33 0.51 c 0.007 0.010 0.19 0.25 d 0.386 0.394 9.80 10.00 e 0.150 0.157 3.80 4.00 e 0.040 0.060 1.02 1.52 h 0.228 0.244 5.80 6.20 l 0.016 0.050 0.40 1.27 0 8 0 8 jedec # : ms-012 e 16l soic (150 mil body) package drawing d h e b a1 a c l seating plane 1

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